1. Technical Field
The present invention relates to a method for manufacturing a semiconductor device having a certain pattern formed with a phase shifting mask.
2. Related Art
In recent years, miniaturization in a gate interconnect pattern is required under a circumstance of increasing integration of semiconductor chips. A patterning process employing a Levenson phase shifting mask is one of effective measures for achieving the above-described miniaturization. Nevertheless, since an use of a Levenson phase shifting mask can only provides a continuous line and space (line/space) pattern, it is necessary for forming a desired pattern to remove unwanted pattern that is created by a Levenson-exposure process.
Typical processes for manufacturing semiconductor devices in the conventional technology include, for example, a technology described in Japanese Patent Laid-Open No. 2000-227,652. Cross-sectional views of a semiconductor device for illustrating a process for manufacturing the semiconductor device described in Japanese Patent Laid-Open No. 2000-227,652 is shown in FIGS. 10A to 10C and FIGS. 11A and 11B.
As shown in FIG. 10A, a gate oxide film 204 is first formed on a silicon substrate 202, and a polycrystalline silicon film 206 are formed thereon. Further, a silicon oxide film 208 for hard mask formation is formed thereon, and then, a positive resist film (not shown) is formed thereon.
A first exposure and developing processes are conducted over such positive resist film through a Levenson phase shifting mask 220. In this case, light is not irradiated over regions of the Levenson phase shifting mask 220 corresponding to an edge of a phase shifter 224 and line-light shielding 222, such that a patterned resist film 210 is formed to have a predetermined geometry (FIG. 10A).
Then, the silicon oxide film 208 is etched through a mask of such resist film 210 to form on polycrystalline silicon film 206 a silicon oxide film 208a, on which a mask pattern is transferred (FIG. 10B). Then, a positive resist film (not shown) is formed so as to cover the polycrystalline silicon film 206 and the silicon oxide film 208a, and then, a second exposure and developing processes are conducted through an exposure mask 226. This provides that only a portion of the silicon oxide film 208a corresponding to the gate pattern to be formed is coated with the protective resist film 212 (FIG. 10C).
Next, rest of the silicon oxide film 208a, which is not coated with the protective resist film 212, is removed via an etch process. Subsequently, the protective resist film 212 is removed to obtain a desired silicon oxide film 208b corresponding to the gate pattern to be formed (FIG. 11A). Then, an etch process for the polycrystalline silicon film 206 is conducted through a mask of such silicon oxide film 208b. This provides a formation of the polycrystalline silicon film 206a, which is a gate pattern corresponding to the silicon oxide film 208b (FIG. 11B).
Nevertheless, there is a room for improvement in the process described in Japanese Patent Laid-Open No. 2000-227,652 that a desired semiconductor device can not obtained since an unexpected pattern is transferred onto the surface of the polycrystalline silicon film 206 in operations illustrated in FIG. 10C and FIG. 11A. This will be further described in reference to FIGS. 12A to 12D.
As shown in FIG. 12A, the second exposure and developing processes are conducted to provide a status, in which only the portions of the silicon oxide film 208a corresponding to the gate pattern to be formed are coated with the protective resist film 212. Next, an etch process for removing unwanted silicon oxide film 208a is conducted. On this occasion, the surface of the exposed polycrystalline silicon film 206 is etched. This causes transferring an unexpected pattern to an exposed portion “A” in the polycrystalline silicon film 206, so that a difference is created in film thickness between the exposed portion “A” and a coated portion “B” with the protective resist film 212 (FIG. 12B).
Next, the polycrystalline silicon film 206 is etched through a mask of the silicon oxide film 208b patterned with a desired hard mask pattern. Since the exposed portion A, which is not coated with the protective resist film 212, is thinner than the coated portion B, which is coated with the protective resist film 212, in the second exposure and developing processes on this occasion, the gate oxide film 204 is first exposed at the exposed portion A (FIG. 12C).
The portion of the polycrystalline silicon film 206a is remained in the coated portion B that is coated with the protective resist film 212, as shown in FIG. 12C, and therefore further etch process is conducted until the gate oxide film 204 is exposed. Such etch process causes an excessive etch for the exposed portion A of the polycrystalline silicon film 206a that is not coated with the protective resist film 212, resulting in proceeding the etching until the gate oxide film 204 is etched, and further proceeding the etching until the silicon substrate 202 is exposed (FIG. 12D).
Further, in recent years, requirements in achieving an increasing operation speed and higher performances of the transistors promote further reduction in the film thickness of the gate oxide film, and thus process allowances for etching the gate oxide film is reduced. Therefore, it is manifested that the etching is proceeded until the silicon substrate is etched, causing a gate leakage current and/or a short-circuit in the obtained semiconductor device.
As described above, when a hard mask disposed on a surface of a first film such as a polycrystalline silicon and composed of a silicon oxide film having an unwanted pattern formed thereon is etched off, the first film may be also etched during the etching for the hard mask, thereby forming an unexpected pattern on the first film. Therefore, an unexpected pattern may be transferred onto the silicon substrate in later operations, causing a generation of a gate leakage current or a short-circuit.